* looking for lethal@linux-sh.org--linux/sh--stable--2.6--patch-515 to compare with * comparing to lethal@linux-sh.org--linux/sh--stable--2.6--patch-515 M arch/sh/boards/renesas/hs7751rvoip/io.c M arch/sh/boards/renesas/hs7751rvoip/setup.c M arch/sh/mm/pmb.c M arch/sh/drivers/pci/pci.c M arch/sh/boards/landisk/io.c M arch/sh/boards/landisk/setup.c M include/asm-sh/io.h M arch/sh/kernel/cf-enabler.c M arch/sh/kernel/setup.c M arch/sh/kernel/sh_ksyms.c M arch/sh/mm/ioremap.c M arch/sh/kernel/io_generic.c M include/asm-sh/mmu.h M arch/sh/boards/renesas/rts7751r2d/io.c M arch/sh/boards/renesas/rts7751r2d/mach.c M arch/sh/boards/titan/io.c M arch/sh/boards/titan/setup.c * modified files --- orig/arch/sh/boards/landisk/io.c +++ mod/arch/sh/boards/landisk/io.c @@ -273,14 +273,6 @@ maybebadio(port); } -void *landisk_ioremap(unsigned long offset, unsigned long size) -{ - if (offset >= 0xfd000000) - return (void *)offset; - - return generic_ioremap(offset, size); -} - void __iomem *landisk_ioport_map(unsigned long port, unsigned int size) { if (PXSEG(port)) --- orig/arch/sh/boards/landisk/setup.c +++ mod/arch/sh/boards/landisk/setup.c @@ -92,7 +92,6 @@ .mv_outsb = landisk_outsb, .mv_outsw = landisk_outsw, .mv_outsl = landisk_outsl, - .mv_ioremap = landisk_ioremap, .mv_ioport_map = landisk_ioport_map, .mv_init_irq = init_landisk_IRQ, #ifdef CONFIG_HEARTBEAT --- orig/arch/sh/boards/renesas/hs7751rvoip/io.c +++ mod/arch/sh/boards/renesas/hs7751rvoip/io.c @@ -295,15 +295,6 @@ maybebadio(outsl, port); } -void *hs7751rvoip_ioremap(unsigned long offset, unsigned long size) -{ - if (offset >= 0xfd000000) - return (void *)offset; - else - return (void *)P2SEGADDR(offset); -} -EXPORT_SYMBOL(hs7751rvoip_ioremap); - unsigned long hs7751rvoip_isa_port2addr(unsigned long offset) { return port2adr(offset); --- orig/arch/sh/boards/renesas/hs7751rvoip/setup.c +++ mod/arch/sh/boards/renesas/hs7751rvoip/setup.c @@ -61,7 +61,6 @@ .mv_outsw = hs7751rvoip_outsw, .mv_outsl = hs7751rvoip_outsl, - .mv_ioremap = hs7751rvoip_ioremap, .mv_isa_port2addr = hs7751rvoip_isa_port2addr, .mv_init_irq = hs7751rvoip_init_irq, }; --- orig/arch/sh/boards/renesas/rts7751r2d/io.c +++ mod/arch/sh/boards/renesas/rts7751r2d/io.c @@ -321,15 +321,6 @@ maybebadio(port); } -void *rts7751r2d_ioremap(unsigned long offset, unsigned long size) -{ - if (offset >= 0xfd000000) - return (void *)offset; - else - return (void *)P2SEGADDR(offset); -} -EXPORT_SYMBOL(rts7751r2d_ioremap); - unsigned long rts7751r2d_isa_port2addr(unsigned long offset) { return port2adr(offset); --- orig/arch/sh/boards/renesas/rts7751r2d/mach.c +++ mod/arch/sh/boards/renesas/rts7751r2d/mach.c @@ -20,7 +20,6 @@ extern void heartbeat_rts7751r2d(void); extern void init_rts7751r2d_IRQ(void); -extern void *rts7751r2d_ioremap(unsigned long, unsigned long); extern int rts7751r2d_irq_demux(int irq); #ifdef CONFIG_USB_SM501 @@ -56,7 +55,6 @@ .mv_outsw = rts7751r2d_outsw, .mv_outsl = rts7751r2d_outsl, - .mv_ioremap = rts7751r2d_ioremap, .mv_init_irq = init_rts7751r2d_IRQ, #ifdef CONFIG_HEARTBEAT .mv_heartbeat = heartbeat_rts7751r2d, --- orig/arch/sh/boards/titan/io.c +++ mod/arch/sh/boards/titan/io.c @@ -138,19 +138,12 @@ maybebadio(port); } -void *titan_ioremap(unsigned long offset, unsigned long size) { - if (CHECK_SH7751_PCIIO(offset) || CHECK_SH7751_PCIMEMIO(offset)) - return (void *)offset; -} - void __iomem *titan_ioport_map(unsigned long port, unsigned int size) { - if (PXSEG(port)) + if (PXSEG(port) || CHECK_SH7751_PCIMEMIO(port)) return (void __iomem *)port; else if (CHECK_SH7751_PCIIO(port)) return (void __iomem *)PCI_IOMAP(port); return (void __iomem *)port2adr(port); } - -EXPORT_SYMBOL(titan_ioremap); --- orig/arch/sh/boards/titan/setup.c +++ mod/arch/sh/boards/titan/setup.c @@ -51,7 +51,6 @@ .mv_insl = titan_insl, .mv_outsl = titan_outsl, - .mv_ioremap = titan_ioremap, .mv_ioport_map = titan_ioport_map, .mv_init_irq = init_titan_irq, --- orig/arch/sh/drivers/pci/pci.c +++ mod/arch/sh/drivers/pci/pci.c @@ -2,7 +2,7 @@ * arch/sh/drivers/pci/pci.c * * Copyright (c) 2002 M. R. Brown - * Copyright (c) 2004, 2005 Paul Mundt + * Copyright (c) 2004 - 2006 Paul Mundt * * These functions are collected here to reduce duplication of common * code amongst the many platform-specific PCI support code files. @@ -172,10 +172,23 @@ return NULL; if (maxlen && len > maxlen) len = maxlen; - if (flags & IORESOURCE_IO) + + /* + * Presently the IORESOURCE_MEM case is a bit special, most + * SH7751 style PCI controllers have PCI memory at a fixed + * location in the address space where no remapping is desired + * (traditionally at 0xfd000000). Once this changes, the + * IORESOURCE_MEM case will have to switch to using ioremap() and + * more care will have to be taken to inhibit page table mapping + * for legacy cores. + * + * For now everything wraps to ioport_map(), since boards that + * have PCI will be able to check the address range properly on + * their own. + * -- PFM. + */ + if (flags & (IORESOURCE_IO | IORESOURCE_MEM)) return ioport_map(start, len); - if (flags & IORESOURCE_MEM) - return ioremap(start, len); return NULL; } --- orig/arch/sh/kernel/cf-enabler.c +++ mod/arch/sh/kernel/cf-enabler.c @@ -42,9 +42,6 @@ #define slot_no 1 #endif -/* defined in mm/ioremap.c */ -extern void * p3_ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags); - /* use this pointer to access to directly connected compact flash io area*/ void *cf_io_base; @@ -63,7 +60,7 @@ return -ENOMEM; } /* printk("p3_ioremap(paddr=0x%08lx, psize=0x%08lx, prot=0x%08lx)=0x%08lx\n", - paddrbase, psize, prot.pgprot, cf_io_base);*/ + paddrbase, psize, prot.pgprot, cf_io_base);*/ /* XXX : do we need attribute and common-memory area also? */ --- orig/arch/sh/kernel/io_generic.c +++ mod/arch/sh/kernel/io_generic.c @@ -215,17 +215,6 @@ ctrl_outl(b, (unsigned long __force)addr); } -void *generic_ioremap(unsigned long offset, unsigned long size) -{ - return (void *)P2SEGADDR(offset); -} -EXPORT_SYMBOL(generic_ioremap); - -void generic_iounmap(void *addr) -{ -} -EXPORT_SYMBOL(generic_iounmap); - void __iomem *generic_ioport_map(unsigned long addr, unsigned int size) { return (void __iomem *)(addr + generic_io_base); --- orig/arch/sh/kernel/setup.c +++ mod/arch/sh/kernel/setup.c @@ -228,9 +228,6 @@ mv_set(readb); mv_set(readw); mv_set(readl); mv_set(writeb); mv_set(writew); mv_set(writel); - mv_set(ioremap); - mv_set(iounmap); - mv_set(ioport_map); mv_set(ioport_unmap); mv_set(irq_demux); --- orig/arch/sh/kernel/sh_ksyms.c +++ mod/arch/sh/kernel/sh_ksyms.c @@ -30,7 +30,6 @@ /* platform dependent support */ EXPORT_SYMBOL(dump_thread); EXPORT_SYMBOL(dump_fpu); -EXPORT_SYMBOL(iounmap); EXPORT_SYMBOL(enable_irq); EXPORT_SYMBOL(disable_irq); EXPORT_SYMBOL(probe_irq_mask); --- orig/arch/sh/mm/ioremap.c +++ mod/arch/sh/mm/ioremap.c @@ -6,13 +6,19 @@ * 640k-1MB IO memory area on PC's * * (C) Copyright 1995 1996 Linus Torvalds + * (C) Copyright 2005, 2006 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file "COPYING" in the main directory of this + * archive for more details. */ - #include +#include #include #include #include #include +#include #include #include @@ -105,10 +111,6 @@ } /* - * Generic mapping function (not visible outside): - */ - -/* * Remap an arbitrary physical address space into the kernel virtual * address space. Needed when the kernel wants to access high addresses * directly. @@ -117,11 +119,11 @@ * have to convert them into an offset in a page-aligned mapping, but the * caller shouldn't need to know that small detail. */ -void * p3_ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags) +void __iomem *__ioremap(unsigned long phys_addr, unsigned long size, + unsigned long flags) { - void * addr; struct vm_struct * area; - unsigned long offset, last_addr; + unsigned long offset, last_addr, addr, orig_addr; /* Don't allow wraparound or zero size */ last_addr = phys_addr + size - 1; @@ -129,10 +131,23 @@ return NULL; /* + * For P1 and P2 space this is trivial, as everything is already + * mapped. Uncached access for P1 addresses are done through P2. + * In the P3 case or for addresses outside of the 29-bit space, + * mapping must be done by the PMB or by using page tables. + */ + if (likely(PXSEG(phys_addr) < P3SEG && PXSEG(last_addr) < P3SEG)) { + if (unlikely(flags & _PAGE_CACHABLE)) + return (void __iomem *)P1SEGADDR(phys_addr); + + return (void __iomem *)P2SEGADDR(phys_addr); + } + + /* * Don't remap the low PCI/ISA area, it's always mapped.. */ if (phys_addr >= 0xA0000 && last_addr < 0x100000) - return phys_to_virt(phys_addr); + return (void __iomem *)phys_to_virt(phys_addr); /* * Don't allow anybody to remap normal RAM that we're using.. @@ -154,16 +169,71 @@ if (!area) return NULL; area->phys_addr = phys_addr; - addr = area->addr; - if (remap_area_pages((unsigned long) addr, phys_addr, size, flags)) { - vunmap(addr); - return NULL; + orig_addr = addr = (unsigned long)area->addr; + +#ifdef CONFIG_32BIT + /* + * First try to remap through the PMB once a valid VMA has been + * established. Smaller allocations (or the rest of the size + * remaining after a PMB mapping due to the size not being + * perfectly aligned on a PMB size boundary) are then mapped + * through the UTLB using conventional page tables. + * + * PMB entries are all pre-faulted. + */ + if (unlikely(size >= 0x1000000)) { + unsigned long mapped = pmb_remap(addr, phys_addr, size, flags); + + if (likely(mapped)) { + addr += mapped; + phys_addr += mapped; + size -= mapped; + } } - return (void *) (offset + (char *)addr); +#endif + + if (likely(size)) + if (remap_area_pages(addr, phys_addr, size, flags)) { + vunmap((void *)orig_addr); + return NULL; + } + + return (void __iomem *)(offset + (char *)orig_addr); } +EXPORT_SYMBOL(__ioremap); -void p3_iounmap(void *addr) +void __iounmap(void __iomem *addr) { - if (addr > high_memory) - vfree((void *)(PAGE_MASK & (unsigned long)addr)); + unsigned long vaddr = (unsigned long __force)addr; + struct vm_struct *p; + + if (PXSEG(vaddr) < P3SEG) + return; + +#ifdef CONFIG_32BIT + /* + * Purge any PMB entries that may have been established for this + * mapping, then proceed with conventional VMA teardown. + * + * XXX: Note that due to the way that remove_vm_area() does + * matching of the resultant VMA, we aren't able to fast-forward + * the address past the PMB space until the end of the VMA where + * the page tables reside. As such, unmap_vm_area() will be + * forced to linearly scan over the area until it finds the page + * tables where PTEs that need to be unmapped actually reside, + * which is far from optimal. Perhaps we need to use a separate + * VMA for the PMB mappings? + * -- PFM. + */ + pmb_unmap(vaddr); +#endif + + p = remove_vm_area((void *)(vaddr & PAGE_MASK)); + if (!p) { + printk(KERN_ERR "%s: bad address %p\n", __FUNCTION__, addr); + return; + } + + kfree(p); } +EXPORT_SYMBOL(__iounmap); --- orig/arch/sh/mm/pmb.c +++ mod/arch/sh/mm/pmb.c @@ -3,7 +3,7 @@ * * Privileged Space Mapping Buffer (PMB) Support. * - * Copyright (C) 2005 Paul Mundt + * Copyright (C) 2005, 2006 Paul Mundt * * P1/P2 Section mapping definitions from map32.h, which was: * @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -127,11 +128,15 @@ return 0; } -void set_pmb_entry(struct pmb_entry *pmbe) +int set_pmb_entry(struct pmb_entry *pmbe) { + int ret; + jump_to_P2(); - __set_pmb_entry(pmbe->vpn, pmbe->ppn, pmbe->flags, &pmbe->entry); + ret = __set_pmb_entry(pmbe->vpn, pmbe->ppn, pmbe->flags, &pmbe->entry); back_to_P1(); + + return ret; } void clear_pmb_entry(struct pmb_entry *pmbe) @@ -162,11 +167,141 @@ clear_bit(entry, &pmb_map); } +static DEFINE_SPINLOCK(pmb_list_lock); +static struct pmb_entry *pmb_list; + +static inline void pmb_list_add(struct pmb_entry *pmbe) +{ + struct pmb_entry **p, *tmp; + + p = &pmb_list; + while ((tmp = *p) != NULL) + p = &tmp->next; + + pmbe->next = tmp; + *p = pmbe; +} + +static inline void pmb_list_del(struct pmb_entry *pmbe) +{ + struct pmb_entry **p, *tmp; + + for (p = &pmb_list; (tmp = *p); p = &tmp->next) + if (tmp == pmbe) { + *p = tmp->next; + return; + } +} + +static struct { + unsigned long size; + int flag; +} pmb_sizes[] = { + { .size = 0x20000000, .flag = PMB_SZ_512M, }, + { .size = 0x08000000, .flag = PMB_SZ_128M, }, + { .size = 0x04000000, .flag = PMB_SZ_64M, }, + { .size = 0x01000000, .flag = PMB_SZ_16M, }, +}; + +long pmb_remap(unsigned long vaddr, unsigned long phys, + unsigned long size, unsigned long flags) +{ + struct pmb_entry *pmbp; + unsigned long wanted; + int pmb_flags, i; + + /* Convert typical pgprot value to the PMB equivalent */ + if (flags & _PAGE_CACHABLE) { + if (flags & _PAGE_WT) + pmb_flags = PMB_WT; + else + pmb_flags = PMB_C; + } else + pmb_flags = PMB_WT | PMB_UB; + + pmbp = NULL; + wanted = size; + +again: + for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++) { + struct pmb_entry *pmbe; + int ret; + + if (size < pmb_sizes[i].size) + continue; + + pmbe = pmb_alloc(vaddr, phys, pmb_flags | pmb_sizes[i].flag); + if (IS_ERR(pmbe)) + return PTR_ERR(pmbe); + + ret = set_pmb_entry(pmbe); + if (ret != 0) { + pmb_free(pmbe); + return -EBUSY; + } + + phys += pmb_sizes[i].size; + vaddr += pmb_sizes[i].size; + size -= pmb_sizes[i].size; + + /* + * Link adjacent entries that span multiple PMB entries + * for easier tear-down. + */ + if (likely(pmbp)) + pmbp->link = pmbe; + + pmbp = pmbe; + } + + if (size >= 0x1000000) + goto again; + + return wanted - size; +} + +void pmb_unmap(unsigned long addr) +{ + struct pmb_entry **p, *pmbe; + + for (p = &pmb_list; (pmbe = *p); p = &pmbe->next) + if (pmbe->vpn == addr) + break; + + if (unlikely(!pmbe)) + return; + + WARN_ON(!test_bit(pmbe->entry, &pmb_map)); + + do { + struct pmb_entry *pmblink = pmbe; + + clear_pmb_entry(pmbe); + pmbe = pmblink->link; + + pmb_free(pmblink); + } while (pmbe); +} + static void pmb_cache_ctor(void *pmb, kmem_cache_t *cachep, unsigned long flags) { + struct pmb_entry *pmbe = pmb; + memset(pmb, 0, sizeof(struct pmb_entry)); - ((struct pmb_entry *)pmb)->entry = PMB_NO_ENTRY; + spin_lock_irq(&pmb_list_lock); + + pmbe->entry = PMB_NO_ENTRY; + pmb_list_add(pmbe); + + spin_unlock_irq(&pmb_list_lock); +} + +static void pmb_cache_dtor(void *pmb, kmem_cache_t *cachep, unsigned long flags) +{ + spin_lock_irq(&pmb_list_lock); + pmb_list_del(pmb); + spin_unlock_irq(&pmb_list_lock); } static int __init pmb_init(void) @@ -177,7 +312,7 @@ BUG_ON(unlikely(nr_entries >= NR_PMB_ENTRIES)); pmb_cache = kmem_cache_create("pmb", sizeof(struct pmb_entry), - 0, 0, pmb_cache_ctor, NULL); + 0, 0, pmb_cache_ctor, pmb_cache_dtor); BUG_ON(!pmb_cache); jump_to_P2(); --- orig/include/asm-sh/io.h +++ mod/include/asm-sh/io.h @@ -249,25 +249,37 @@ * differently. On the x86 architecture, we just read/write the * memory location directly. * - * On SH, we have the whole physical address space mapped at all times - * (as MIPS does), so "ioremap()" and "iounmap()" do not need to do - * anything. (This isn't true for all machines but we still handle - * these cases with wired TLB entries anyway ...) + * On SH, we traditionally have the whole physical address space mapped + * at all times (as MIPS does), so "ioremap()" and "iounmap()" do not + * need to do anything but place the address in the proper segment. This + * is true for P1 and P2 addresses, as well as some P3 ones. However, + * most of the P3 addresses and newer cores using extended addressing + * need to map through page tables, so the ioremap() implementation + * becomes a bit more complicated. See arch/sh/mm/ioremap.c for + * additional notes on this. * * We cheat a bit and always return uncachable areas until we've fixed * the drivers to handle caching properly. */ -static inline void *ioremap(unsigned long offset, unsigned long size) -{ - return sh_mv.mv_ioremap(offset, size); -} - -static inline void iounmap(void *addr) -{ - return sh_mv.mv_iounmap(addr); -} - -#define ioremap_nocache(off,size) ioremap(off,size) +#ifdef CONFIG_MMU +void __iomem *__ioremap(unsigned long offset, unsigned long size, + unsigned long flags); +void __iounmap(void __iomem *addr); +#else +#define __ioremap(offset, size, flags) (offset) +#define __iounmap(addr) do { } while (0) +#endif /* CONFIG_MMU */ + +#define ioremap(offset, size) \ + __ioremap((offset), (size), 0) +#define ioremap_nocache(offset, size) \ + __ioremap((offset), (size), 0) +#define ioremap_cache(offset, size) \ + __ioremap((offset), (size), _PAGE_CACHABLE) +#define p3_ioremap(offset, size, flags) \ + __ioremap((offset), (size), (flags) +#define iounmap(addr) \ + __iounmap((addr)) static inline int check_signature(char __iomem *io_addr, const unsigned char *signature, int length) @@ -285,9 +297,6 @@ return retval; } -/* arch/sh/mm/ioremap.c */ -void *p3_ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags); - /* * The caches on some architectures aren't dma-coherent and have need to * handle this in software. There are three types of operations that --- orig/include/asm-sh/mmu.h +++ mod/include/asm-sh/mmu.h @@ -50,6 +50,8 @@ #define PMB_NO_ENTRY (-1) +struct pmb_entry; + struct pmb_entry { unsigned long vpn; unsigned long ppn; @@ -60,16 +62,23 @@ * PMB_NO_ENTRY to search for a free one */ int entry; + + struct pmb_entry *next; + /* Adjacent entry link for contiguous multi-entry mappings */ + struct pmb_entry *link; }; /* arch/sh/mm/pmb.c */ int __set_pmb_entry(unsigned long vpn, unsigned long ppn, unsigned long flags, int *entry); -void set_pmb_entry(struct pmb_entry *pmbe); +int set_pmb_entry(struct pmb_entry *pmbe); void clear_pmb_entry(struct pmb_entry *pmbe); struct pmb_entry *pmb_alloc(unsigned long vpn, unsigned long ppn, unsigned long flags); void pmb_free(struct pmb_entry *pmbe); +long pmb_remap(unsigned long virt, unsigned long phys, + unsigned long size, unsigned long flags); +void pmb_unmap(unsigned long addr); #endif /* __MMU_H */